Fishing – trapping – and vermin destroying
Patent
1991-11-12
1994-01-25
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437203, H01L 21265
Patent
active
052815471
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method for manufacturing a field effect transistor (hereinafter referred in some cases to simply as "FET" (: Field Effect Transistor) which is suitably used with respect to various LSIs (: Large Scale Integrated Circuit). More particularly, the invention relates to a technology improving the degree of integration by utilizing a wall which extends between the two surface levels involved in the base layer.
BACKGROUND TECHNOLOGY
To increase the degree of integration of LSIs, it is necessary to reduce the area occupied on the main surface of the substrate by the individual semiconductor elements which constitute an LSI.
FIG. 3(A) to 3(C) are schematic views illustrating a conventionally most widely known structure of MOS (Metal Oxide Semiconductor) type FET (hereinafter referred in some cases to simply as "MOSFET"). Namely, FIG. 3(A) is a plan view, as taken from above, of an essential portion of the semiconductor device; FIG. 3(B) is a sectional view taken along the one-dot chain line I--I of FIG. 3(A); and FIG. 3(C) is a sectional view taken along the one-dot chain line II--II of FIG. 3(A). In these Figures, only one element is shown and the hatching, etc. indicating sectional views are partially omitted. Further, in order to make it easier to understand the following descriptions, impurity diffusion regions for forming source and drain are referred as a "source region" and a "drain region" which are shown in a specified disposition relationship. However, this disposition relationship is only illustrative. Therefore, the function of the element is not impaired whatsoever even when the illustrated dispositions of the two regions have been reversed.
As well known, the MOSFET structure shown in these figures is the most basic structure among those of conventional elements, in which the voltage applied to a gate electrode 11 is used as a control signal for electrically switching a current passing between a source region 13 and a drain region 15.
First, as shown in FIG. 3(A), the gate electrode 11 is formed with a width W1 corresponding to disposition dimension of one element and is also formed with a length l1 in the shape of a stripe. Each element is electrically isolated from another by means of a field oxide film 17.
As shown in FIGS. 3(B) and 3(C), the element of this type uses a substrate 19 made of silicon, as a base layer, the above-mentioned gate electrode 11 being disposed on this substrate 19 via a gate insulating film 21. The above-mentioned source region 13 and drain region 15 are provided as independent constituent elements, respectively, on both sides of the gate electrode 11 (and the gate insulating film 21).
Usually, the gate length l1 is set at approximately 0.5 to 1.0 (.mu.m). Since the electric current passing between the source and the drain corresponding to the driving ability of the element is in proportional relation to the gate width W1, it is considered to be optimal that this width W1 is approximately ten times as large as the gate length l1, in consideration of the operating speed of the element. Accordingly, the width W1 is set at approximately 5 to 10 (.mu.m).
With an increase in the degree of integration of LSI, an attempt has been made to decrease the gate length l1 and the gate width W1. However, since both the l1 and W1 are set by utilizing the main surface of the substrate as the base layer in a two-dimensional manner, dimensional decreasing of the l1 and W1 is limited when considering that the above-mentioned driving ability and operating speed of the element should be maintained.
Under the above-mentioned existing circumstances, various proposals have been made as to the technology improving the degree of integration without impairing the function of the element. For instance, Japanese Laid Open Patent Publication No. 61-206253 discloses a technique enlarging the surface area effective to form the element by three-dimensional utilization of the base layer.
Another prior art technique disclosed in this publication will here
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A Model for the Trench Transistor, S. Banerjee et al., IEEE Transactions on Electron Devices, vol. ED-34, No. 12, Dec. '87, pp. 2485-2492.
IBM Technical Disclosure Bulletin, vol. 29, No. 10, Mar., 1987, "Trench Mosfets (3D Structure)", pp. 4305-4307.
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Hayashi Takahisa
Ochiai Toshiyuki
Uchiyama Akira
Fleck Linda J.
Hearn Brian E.
OKI Electric Industry Co., Ltd.
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