Semiconductor memory

Static information storage and retrieval – Format or disposition of elements

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365189, G11C 1140

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active

046758453

ABSTRACT:
A semiconductor memory having a structure wherein each of data lines intersecting word lines is divided into a plurality of sub lines in its lengthwise direction, memory cells are arranged at the points of intersection between the divided sub lines and the word lines, common input/output lines are disposed in common to a plurality of such sub lines, the common input/output lines and the plurality of sub lines are respectively connected by switching elements, and the switching elements are connected to a decoder through control lines and are selectively driven by control signals generated from the decoder.

REFERENCES:
patent: 4122546 (1978-10-01), Von Basse et al.
patent: 4316265 (1982-02-01), Tanaka et al.
patent: 4357685 (1982-11-01), Daniele et al.
patent: 4408305 (1983-10-01), Kuo
patent: 4590588 (1986-05-01), Itoh et al.
1981 IEEE International Solid State Circuits Conference, "Memories and Redundancy Techniques", Eaton et al, 2-18-81, pp. 84-85.

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