Water-scale-integrated assembly

Details Water-scale-integrated assembly Water-scale-integrated assembly

1984-10-09

1987-06-23

Edlow, Martin H.

357 51, 357 45, 357 40, 357 80, H01L 2348

Patent

active

046757171

ABSTRACT:
The standard silicon wafer of a conventional wafer-scale-integrated assembly is doped to render it highly conductive. Additionally, a conductive layer is formed on the bottom of the wafer. The bottom-side layer forms an easily accessible ground plane of the assembly. Moreover, this layer and the conductive silicon constitute one plate of an advantageous wafer-size decoupling capacitor. A nearly continuous power layer and a relatively thick layer of silicon dioxide on the top side of the assembly form the other elements of the decoupling capacitor. Additionally, the nearly continuous power layer constitutes an effective a-c ground plane for overlying signal lines.

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Bodendorf et al, "Active Silicon Chip Carrier", IBM Technical Disclosure Bulletin, vol. 15, No. 2, Jul. 1972, pp. 656-657.
Kraynak et al, "Wafer-Chip Assembly for Large-Scale Integration," IEEE Transactions on Electron Devices, vol. ED-15, No. 9, Sep. 1968, pp. 660-663.
D. L. Peltzer, "Wafer-Scale Integration: The Limits of VLSI?", VLSI Design, Sep. 1983, pp. 43-47.
C. Huang, "Silicon Packaging-A New Packaging Technique", IEEE Custom Integrated Circuits Conference, Rochester, New York, May 24, 1983, pp. 142-146.
Y. Egawa et al, "A 1-Mbit Full-Wafer MOS RAM," IEEE Transactions on Electron Devices, vol. ED--27, No. 8, Aug. 1980, pp. 1612-1621.

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