Nonvolatile semiconductor system

Details Nonvolatile semiconductor system Nonvolatile semiconductor system

1993-11-08

1995-03-14

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

36518901, 365218, G11C 1134, G11C 700

Patent

active

053982045

ABSTRACT:
It is an object of the invention to provide a nonvolatile semiconductor system, particularly a flash (entire array erasure) type EEPROM, of which reading operation can be prevented from failing even if any one memory transistor is overerased. When the data reading operation is carried out for a memory transistor 1, an N-channel transistor 6 is turned off, and P-channel transistors 7 and 8 are also turned off, since a word line WL2 is at GND level. Even if a memory transistor 3 is overerased, for example, a drain current can be prevented from flowing from a bit line BL1 to a source power, which also prevents wrong reading operation. Even if any one memory transistor is overerased and not selected, a wrong reading operation can be prevented since no electric current flows from the bit line. Thus, any means for preventing the overerasing, such as verifying operation means or the like, is not required.

REFERENCES:
patent: 4949309 (1990-08-01), Rao
patent: 5185718 (1993-02-01), Rinerson et al.
patent: 5241507 (1993-08-01), Fong

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