Parity bit lock-on method and apparatus

Details Parity bit lock-on method and apparatus Parity bit lock-on method and apparatus

1981-10-15

1983-10-25

Atkinson, Charles E.

Excavating

371 42, 371 49, 375106, H04L 702

Patent

active

044123299

ABSTRACT:
Method and apparatus for locking onto the parity bit of a bit stream of equal length words, each of which words includes a parity bit, are disclosed. The bit stream is shifted through a data shift register which includes a plurality of word length sections. Parity of bits contained in the first section of the data shift register is checked every bit interval of the bit stream. Two parity bit shift registers are provided, the first of which is one word in the length and the second of which is of the same length as the data shift register. The output from the parity checking means is connected to serial inputs of said first and second parity bit shift registers through a logic gate controlled by the serial output from the first parity bit shift register. When the serial output from the first parity bit shift register is a "one" bit, the results of the parity check are entered into said first and second parity bit shift registers through said logic gate, and when the serial output therefrom is a "zero" bit, a "zero" bit is entered into said first and second parity bit shift registers. Means are provided for connecting parallel outputs of said second parity bit shift register to a decision logic circuit having a word clock pulse output which is synchronized with parity bits in the bit stream when the apparatus is locked onto parity bits in the stream.

REFERENCES:
patent: 3587043 (1971-06-01), Mengani
patent: 3842399 (1974-10-01), Kneuer et al.
patent: 3938086 (1976-02-01), Valbonesi
patent: 4361898 (1982-11-01), Griffiths et al.

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