Test circuit

Details Test circuit Test circuit

1996-12-17

1999-09-28

Beausoliel, Jr., Robert W.

Excavating

365201, G01R 3128

Patent

active

059600080

ABSTRACT:
In a normal operation, a shift mode signal (SM) is set to "0" to propagate signals applied to "0"-input ends of selectors (10 to 12), i.e., outputs of a logic unit (80). In a logic scan test on logic units (80, 81), by setting a test-mode signal to "1", an ordinary scan test is performed with a scan path of simple configuration, having bits as much as write data and employing scan flip flops consisting of pairs of selectors (10 to 12) and flip flops (30 to 32) respectively. The flip flops used for writing in the normal operation can be also used as those used for the scan flip flops in the logic test. Thus, a configuration of the scan path to achieve excellent area-efficiency is provided.

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patent: 5588006 (1996-12-01), Nozuyama
patent: 5617428 (1997-04-01), Andoh
patent: 5621740 (1997-04-01), Kamada
patent: 5726998 (1998-03-01), Ozaki
patent: 5729553 (1998-03-01), Motohara

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