Syndrome processing unit for multibyte error correcting systems

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G06F 1110

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045049483

ABSTRACT:
A syndrome processing unit for a multibyte error correcting system is disclosed in which logical circuitry for performing product operation on selected pairs of 8-bit syndrome bytes and exclusive-OR operations on selected results of the product operations are selectively combined to define usable cofactors that correspond to coefficients of an error locator polynomial corresponding to a selected codeword if the codeword contains less than the maximum number of errors for which the system has been designed.

REFERENCES:
patent: 4388684 (1983-06-01), Nibby, Jr. et al.
patent: 4413339 (1983-11-01), Riggle et al.
patent: 4453251 (1984-06-01), Osman
patent: 4455655 (1984-06-01), Galen et al.

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