Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-05-30
1999-09-28
Phan, Trong
Static information storage and retrieval
Addressing
Sync/clocking
3652335, 36518909, 36518911, 365194, G11C 800, G11C 700
Patent
active
059599359
ABSTRACT:
The invention refers to a generating circuit for synchronization signals to regulate the read phase of memory cells in electronic devices with an integrated memory on a semiconductor, of the type controlled by a switching of logical states on a left ATD bus and a right ATD bus and comprising a left and a right section inserted between a first and a second voltage reference and connected respectively to the left and the right ATD bus, the sections being connected at the input to a reference-voltage generated and at the output to an ATD generator. Each of the sections of the generating circuit according to the invention includes a pull-up transistor inserted between the first voltage reference and a first internal circuit node and having a control terminal connected to a polarization structure suitable for modifying the conductivity of pull-up transistors, intentionally reduced in the coupling phase to assure capture of all transitions on the left and right ATD buses, and increased in the operating phase to follow with precision the events of the transition, guiding the read phase in a timely manner.
REFERENCES:
patent: 4811299 (1989-03-01), Miyazawa et al.
patent: 5177393 (1993-01-01), Miyazawa et al.
patent: 5473574 (1995-12-01), Clemen et al.
patent: 5532972 (1996-07-01), Passcucci et al.
patent: 5663921 (1997-09-01), Passcucci et al.
Carlson David V.
Phan Trong
SGS--Thomson Microelectronics S.r.l.
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