Method for operating nonvolatile memory semiconductor devices me

Details Method for operating nonvolatile memory semiconductor devices me Method for operating nonvolatile memory semiconductor devices me

1993-04-30

1995-04-18

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 1604

Patent

active

054084300

ABSTRACT:
The present invention provides method for erasing a flash memory wherein "overerasing" can be prevented. To erase the cell, a gate voltage of 3 volts is applied to a control gate electrode and a voltage of 15 volts is applied to a source. A drain is left floating. At that time, the accumulated electrons begin to be injected from the floating gate to the source by tunneling. The threshold voltage of the flash memory cell decreases into less than 3 volts in the erasing operation, the potential difference between the floating gate and the source decreases. This enables the amount of charge by F-N tunneling to decrease and the erasing speed to decrease accordingly.

REFERENCES:
patent: 4377857 (1983-03-01), Tickle
patent: 5047981 (1991-09-01), Gill et al.

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