MPEG-2 transport stream decoder having decoupled hardware archit

Details MPEG-2 transport stream decoder having decoupled hardware archit MPEG-2 transport stream decoder having decoupled hardware archit

1995-11-06

1999-09-28

Chin, Tommy P.

Television

Special applications

Manufacturing

348423, 455 42, H04N 7173

Patent

active

059596597

ABSTRACT:
An MPEG-2 decoder having a decoupled architecture that allows the rapid acquisition of a program within an MPEG-2 transport stream. A digital signal processor (102) is provided to demultiplex a MPEG-2 transport stream provided on a line (110) into its constituent audio, video, and private data elementary streams. The digital signal processor is capable of performing a limited interpretation of program specific information in the transport stream data, prior to presentation of the program specific information to a host microprocessor (106). In particular, the digital signal processor can demultiplex and interpret back-to-back program association tables and program map tables carried in the transport stream. In the absence of a user selected program, the digital signal processor selects a default program to demultiplex and display to the user. The host microprocessor runs an operating system of the decoder, generates a user interface, and allows the user to select from the programs within the transport stream. Hardware framing logic (114) is also provided to generate and provide to the digital signal processor synchronizing bytes that correspond to the start of each transport packet within the transport stream.

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Coding of Moving Pictures and Associated Audio: Systems (ISO/IEC JTC1/SC 29/WG11 N0801, Published on Nov. 13, 1994, by the ISO/IEC Copyright Office, Geneva, Switzerland).

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