Cryptography – Communication system using cryptography – Data stream/substitution enciphering
Patent
1985-09-25
1987-05-26
Cangialosi, Salvatore
Cryptography
Communication system using cryptography
Data stream/substitution enciphering
380 44, 380 46, 380 47, H04K 102, H04L 904
Patent
active
046691189
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a self-synchronizing descrambler comprising n clocked shift register stages for descrambling a signal having a scrambler period of 2.sup.n -1 bits, whereby the output of at least one shift register stage is connected to the input of at least one modulo-2 adder.
2. Description of the Prior Art
Pulse patterns having a disturbing DC component or a particularly high energy component at other, discrete frequencies can occur in digital signal transmission insofar as involved recodings are not undertaken. In order to avoid these patterns, the digital signal to be transmitted is scrambled at the transmitting side by a modulo-2 addition with a pseudo-random sequence. The descrambling occurs at the receiving side by a further modulo-2 addition with the pseudo-random sequence employed at the transmitting side. The synchronization of the pseudo-random generators employed at the transmitting and receiving side which is thereby necessary can be avoided by employing free-wheeling and, therefore, self-synchronizing scrambler and descrambler arrangements.
With the further expansion of the digital telecommunications system, the necessity of constructing the scrambler arrangement and the descrambler arrangement for digital signals having the high transmission rate arises.
"Siemens Forschungs-und Entwicklungsberichte", Vol. 6, No. 1, 1977, pp. 1-5, fully incorporated herein by this reference, discloses a possibility for constructing scrambler and descrambler arrangements for pulse code modulated (PCM) signals having a high clock frequency. The PCM signals are thereby scrambled in a plurality of parallel channels having a comparatively lower bit repetition frequency and the scrambled signals are combined to form the transmission signal by multiplexing. The demultiplexer is analogously provided at the receiving side, the parallel descrambling in a plurality of channels having a low bit repetition frequency following thereat. In addition to the high expense, the necessity of synchronizing multiplexers and demultiplexers with one another occurs in such a solution.
SUMMARY OF THE INVENTION
The object of the present invention, therefore, is to provide self-synchronizing descramblers for the transmission of digital signals having a high bit repetition frequency, the expense of these descramblers being reduced particularly by omitting a demultiplexer.
The above object is achieved, according to the present invention, in a self-synchronizing descrambler of the type initially set forth and which is particularly characterized in the n parallel inputs for respectively one of n parallel bits of the scrambled digital signal are provided; in that the inputs are ordered corresponding to the sequence of incoming bits with the n.sup.th bit at the first input and the following bits at the next inputs and are connected to a respective scrambler stage; and in that the descrambler stages respectively contain a shift register stage as well as first and second modulo-2 adders. The descrambler is further characterized in that the output of the shift register stage is connected to the first input of the first modulo-2 adder and the output of the first modulo-2 adder is connected to the first input of the second modulo-2 adder; in that the second input of the second modulo-2 adder is connected to the assigned input for the scrambled digital signal and to the input of the shift register stage contained in the same descrambler stage; and in that the output of the second modulo-2 adder represents the output of the respective scrambler stage for the descrambled digital signal. The descrambler is further characterized in that, in all descrambler stages up to the (n-m+1).sup.th, the second input of the first modulo-2 adder of the one descrambler stage is connected to the output of the shift register stage of the descrambler stage for the m.sup.th bit; in that m is smaller than n and is a whole number, in that, at the (n-m).sup.th descrambler stage, a connection occurs f
REFERENCES:
patent: 4434322 (1984-02-01), Ferrell
Elektronik, vol. 32, No. 26, (12/30/83) Munich (DE) Hermes et al, "Parallel . . . Scrambler . . . pp. 67-70 (see 68).
Cangialosi Salvatore
Siemens Aktiengesellschaft
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