High speed counter with decoding means and means for selecting s

Details High speed counter with decoding means and means for selecting s High speed counter with decoding means and means for selecting s

1985-12-16

1987-05-26

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Particular output circuits for counter

377116, 377 41, 307272A, H03K 2116

Patent

active

046691014

ABSTRACT:
A counter for counting clock pulses and having a plurality of output bits successively numbered from a first output bit to a highest output bit. The counter includes a plurality of bistable devices, one bistable device being associated with each output bit, and each bistable device including a clock input for receiving clock pulses to be counted, and an output for providing one of the output bits and its complement. The bistable device which is associated with the first output bit toggles with the receipt of each clock pulse to be counted. The counter also includes a decode section responsive to the outputs of the plurality of bistable devices for providing decoded signals, and a select section for receiving the clock pulses to be counted and responsive to the decoded signals and the complement of the first output bit. The select section selects which of the plurality of bistable devices associated with the second and higher output bits will toggle on the receipt of the next clock pulse. The plurality of bistable devices, the decode section, and the select section operate in parallel with one another.

REFERENCES:
patent: 2816223 (1957-12-01), Nelson
patent: 2848166 (1958-08-01), Wagner
patent: 4072904 (1978-02-01), Casner et al.
patent: 4291241 (1981-09-01), Mayama et al.
patent: 4408336 (1983-10-01), Dasgupta

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