Semiconductor memory device with bit line and select line arrang

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

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257776, 365 69, 365 51, 365 63, G11C 702, G11C 506

Patent

active

056252340

ABSTRACT:
A semiconductor memory device in which sensing of the memory information stored in a memory cell can be carried out stably, and reliably by equilibrating a parasitic capacitance existing between a select line and its adjacent bit line pair. Each Y select line YS is arranged at a position where it uniformly spans over both members of a bit line pair which extend straight in parallel to each other without the twist part TW within an area of four bit line pairs (eight bit lines or auxiliary bit lines) that are simultaneously sensed. Within an area of the first set of bit line pairs (BL0,BL0-)-(BL3,BL3-), in addition to the bit line pair (BL1,BL1-), the line pairs (BL0,BL0-) and (BL2,BL2-) with the twist part TW are substantially capacitance-coupled with the Y select line YS0. In these bit line pairs, the parasitic capacitance for the Y select line YS0 is at equilibrium between a bit line and an auxiliary bit line.

REFERENCES:
patent: 4922459 (1990-05-01), Hidaka
patent: 4977542 (1990-12-01), Matsuda et al.
patent: 5062077 (1991-10-01), Takashima et al.
patent: 5088064 (1992-02-01), Tsukude et al.
patent: 5144583 (1992-09-01), Oowaki et al.

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