Dual-node capacitor coupled MOSFET for improving ESD performance

Details Dual-node capacitor coupled MOSFET for improving ESD performance Dual-node capacitor coupled MOSFET for improving ESD performance

1998-01-24

1999-09-28

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327318, 327566, H03K 508

Patent

active

059594888

ABSTRACT:
A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time, the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.

REFERENCES:
patent: 4423431 (1983-12-01), Sasaki
patent: 5528188 (1996-06-01), Au et al.
patent: 5631793 (1997-05-01), Ker et al.
patent: 5686751 (1997-11-01), Wu
patent: 5721656 (1998-02-01), Wu et al.
patent: 5818086 (1998-10-01), Lin et al.
patent: 5852541 (1998-12-01), Lin et al.

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