CCD imager with JFET peripherals

Electrical pulse counters – pulse dividers – or shift registers: c – Counting or dividing in incremental steps – Beam type tube

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357 22, 357 30, 357 91, 377 60, 377 62, H01L 2978, H01L 2714, H01L 3100, G11C 1928

Patent

active

046689710

ABSTRACT:
A CCD imager wherein a mixed MOSFET and JFET periphery is provided using the same device doping profiles as are used for fabrication of the CCD structure. This provides simple fabrication of low-noise amplifiers integrated with the CCD array. Preferably the gate of the JFET is formed with the same implant which forms the virtual phase electrode in an array of virtual phase CCD cells. Preferably the JFETs are used as loads in source-follower stages. Preferably the MOSFET devices include both buried-channel and surface-channel devices connected to a common drain voltage; the buried-channel devices are used for earlier stages of amplification, where they can be operated in their low-noise regime, and the surface channel used for output stages. If buried channel devices were used for the output stage, then the buried-channel devices in the prior stage would have to be biased into a high-noise regime to achieve the necessary output voltage swings.

REFERENCES:
patent: 4032952 (1977-06-01), Ohba et al.
patent: 4229752 (1980-10-01), Hynecek
patent: 4513313 (1985-04-01), Kinoshita et al.
Dawson et al., "A CMOS/Buried-N-Channel CCD Compatible Process for Analog Signal Processing Applications", RCA Review, vol. 38 (9/77), pp. 406-435.

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