Method of fabricating field effect transistors

Details Method of fabricating field effect transistors Method of fabricating field effect transistors

1983-01-28

1985-03-12

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 29579, 148187, H01L 21265

Patent

active

045035997

ABSTRACT:
Herein disclosed is a field effect transistor fabricating method comprising: the step of forming a surface portion of a semiconductor substrate with an impurity region for a channel; the step of forming a first material layer, which has a width substantially equal to that of a gate electrode, in such a position on said semiconductor substrate and is to be formed with said gate electrode, a second material layer, which has a width larger than that of said first material layer, above said first material layer, and source and drain regions by an ion implantation using said first and second material layers thus formed as a mask; the step of forming source and drain electrodes in contact with said source and drain regions; the step of forming a third material layer, which has a selectivity with said first material layer in its etched characteristics, on the semiconductor body thus far prepared by the foregoing steps; the step of forming at least an aperture by removing said first material layer in a state using said third material layer as a mask; and the step of forming said gate electrode in said aperture.

REFERENCES:
patent: 4033788 (1977-07-01), Hunsperger et al.
patent: 4173063 (1979-11-01), Kniepkamp et al.
patent: 4252580 (1981-02-01), Messick
patent: 4266333 (1981-05-01), Reichert
patent: 4312112 (1982-01-01), Calviello
patent: 4325181 (1982-04-01), Yoder
patent: 4368573 (1983-01-01), de Brebisson et al.
patent: 4377030 (1983-03-01), Pettenpaul et al.
Mar et al., Solid State Technology, "Properties of Plasma Enhanced CVD Silicon Nitride: Measurements and Interpretations", Apr. 1980, pp. 137-142.

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