Method of forming a planarized insulation layer

Details Method of forming a planarized insulation layer Method of forming a planarized insulation layer

1992-12-08

1994-02-08

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

257637, 257641, 257647, H01L 2934, H01L 2904

Patent

active

052851028

ABSTRACT:
A method for forming a planar insulating layer over the surface of a semiconductor workpiece 8 which includes at least one low region 13 is discussed herein. The first step is to form a layer of blocking material 14 on the surface of the workpiece 8. A first material region 20 is then formed in the low region 13 and an insulating layer 21 is formed over the surface of the workpiece 8 including the first material region 20. The workpiece 8 is then heated in the presence of an active ambient such that the insulation layer 21 reflows and also so that the first material 20 region reacts with the active ambient to create an internal stress in said insulation layer 21. Other systems and methods are also disclosed.

REFERENCES:
patent: 4239559 (1980-12-01), Ito
patent: 4982250 (1991-01-01), Manos, II et al.
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5068711 (1991-11-01), Mise
B. E. Deal, "Historical Perspectives of Silicon Oxidation" in The Physics and Chemistry of SiO.sub.2 and the Si-SiO.sub.2 Interface, Edited by C. Robert Helms and B. E. Deal, pp. 5-15 (1988).
Sze, S. M., Semiconductor Devices Physics and Technology, 1985, pp. 341-354.

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