Method and apparatus for scan chain with reduced delay penalty

Details Method and apparatus for scan chain with reduced delay penalty Method and apparatus for scan chain with reduced delay penalty

1997-03-17

1998-11-03

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058319930

ABSTRACT:
A method is provided for operating a scan chain in a semiconductor device having a plurality of serially connected logic blocks, an output from a first logic block being coupled to an input of a first latch, the output from the first latch being coupled to the input of a second logic block, an output of the second logic block being coupled to an input of a second latch, the method comprising: detecting a test enable signal; if the test enable signal is active: detecting the output of the first latch, and setting the output of the second latch to the same state as the detected output of the first latch, independently of the state of the output of the second logic block; if the test enable signal is inactive: setting the output of the second latch responsive to the output of the second logic block.

REFERENCES:
patent: 5640404 (1997-06-01), Satish
patent: 5694402 (1997-12-01), Butler et al.

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