Patent
1995-10-25
1998-09-29
Sheikh, Ayaz R.
395309, 39520043, 39520044, 39580021, 39580022, H01J 1300
Patent
active
058156801
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a multiprocessor, which is one kind of processors used for the digital signal processing mainly dealing with voice information, image information and the like, and which performs an parallel execution on multiple datapath elements.
BACKGROUND ART
In the field of the signal processing for the voices and images, it is frequently occurred that a simple calculation is repeatedly performed on a plenty of numerical data in order to perform the correlation calculation and the like. In such field of application, by using the multiprocessor according to a certain system (i.e., single-instruction multiple-data-stream (SIMD) system) in which multiple datapath elements, each having the same structure, operate in parallel by the same instruction, it is possible to perform the operational processing at high speed and with high efficiency.
FIG. 11 is a block diagram showing a structural example for a main part of the multiprocessor according to the conventional single-instruction multiple-data-stream system. In this figure, `N` (where N.gtoreq.2) datapath elements 1.sub.1 to 1.sub.N and `N` local memories 2.sub.1 to 2.sub.N for storing data are connected with a interconnection network 3; hence, data are mutually exchanged between the datapath elements 1.sub.1 -1.sub.N and the local memories 2.sub.1 -2.sub.N as well as among the datapath elements 1.sub.1 -1.sub.N ; a control element 4 precisely manages states of the datapath elements 1.sub.1 -1.sub.N and the interconnection network 3 so as to instruct them an appropriate procedure of calculation and an appropriate procedure of operations when executing the instruction. Incidentally, each of the local memories 2.sub.1 -2.sub.N has an address space whose size is indicated by `M`, while a necessary address number is given from an address generating unit which is not shown in the figure.
In the configuration of FIG. 11, there are provided multiple local memories 2.sub.1 -2.sub.N the number of which is equal to the number of the datapath elements 1.sub.1 -1.sub.N ; and, when performing the parallel operation, each of the datapath elements can simultaneously access to each of the local memories; therefore, at this time, the interconnection network 3 interconnects the datapath elements 1.sub.1 -1.sub.N and the local memories 2.sub.1 -2.sub.N respectively in one-by-one connection manner.
In addition, the control regarding the procedure of calculation is concentrated to the control element 4; therefore, it is not necessary to provide an instruction decoder and an arithmetic-control circuit with respect to each of the datapath elements; hence, even when the number of the datapath elements is increased in order to improve the performance of processing, it is possible to reduce the scale of the control circuit against the whole circuitry. Further, by singularizing the instruction steam, it is not necessary to provide multiple control fields, the number of which corresponds to the number of the datapath elements, in the instruction; as a result, it is possible to shorten the instruction word-length; hence, the capacity of the memory for storing the instructions in the programs having a plenty of steps can be remarkably reduced. Incidentally, the interconnection network 3 is a data exchange circuit which constructs a necessary connection pattern with respect to each kind of the calculation; however, in order to realize a more complex calculation in which the result of calculation in another datapath element is referred to, a flexibility in which more varied interconnection patterns are constructed is required for the interconnection network.
In the conventional multiprocessor whose structure is represented by the above-mentioned structure, in order to realize the interconnection between each datapath element and each local memory by a more number of connection patterns, the scale of circuit and the complexity of control for the interconnection network 3 should be increased; particularly when executing a complex calculation which requ
REFERENCES:
patent: 5471592 (1995-11-01), Gove et al.
patent: 5533201 (1996-07-01), Benton et al.
patent: 5537569 (1996-07-01), Masubuchi
patent: 5559970 (1996-09-01), Sharma
patent: 5581767 (1996-12-01), Katsuki et al.
patent: 5613138 (1997-03-01), Kishi et al.
patent: 5617538 (1997-04-01), Heller
Miki Toshio
Miki Yoshinori
Ohya Tomoyuki
Okumura Yukihiko
Johnson John T.
NTT Mobile Communications Network Inc.
Phan Raymond N.
Sheikh Ayaz R.
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