PLL frequency synthesizer having circuit for controlling gain of

Details PLL frequency synthesizer having circuit for controlling gain of PLL frequency synthesizer having circuit for controlling gain of

1997-01-29

1998-11-03

Nelms, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 25, H03L 700

Patent

active

058314830

ABSTRACT:
A PLL frequency synthesizer has a detecting circuit 7 integrating a difference of an up signal and a down signal down, and outputting a control signal Vg according to the difference, and a charge circuit 5 receiving the control signal Vg, up signal and down signal, charging an output node by a first current ability when the control signal Vg is at a high level and the up signal and the down signal are at high level and at low level, respectively, discharging the output node by first current ability when the control signal Vg is at high level and the up signal and the down signal are at low level and at high level, respectively, charging the output node by second current ability lower than first current ability when the control signal Vg is at high level and the up signal and the down signal are at high level and at low level, respectively, and discharging the output node by second current ability when the control signal is at low level and the up signal and the down signal are at low level and high level.

REFERENCES:
patent: 4156855 (1979-05-01), Crowley
patent: 4745372 (1988-05-01), Miwa
patent: 5126692 (1992-06-01), Shearer et al.
patent: 5276408 (1994-01-01), Norimatsu
patent: 5334951 (1994-08-01), Hogeboom
patent: 5475326 (1995-12-01), Masuda

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