PDH/SDH signal processor with dual mode clock generator

Details PDH/SDH signal processor with dual mode clock generator PDH/SDH signal processor with dual mode clock generator

1996-05-13

1998-09-29

Marcelo, Melvin

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

370518, 375376, H04J 306

Patent

active

058155040

ABSTRACT:
A signal processor comprises a first circuit for extracting a PDH (plesiochronous digital hierarchy) signal from an incoming SDH (synchronous digital hierarchy) signal and a second circuit for adding an overhead to an incoming pure SDH signal to produce a synchronous transport module (STM) output signal. The output of the first circuit is selected when the incoming signal contains the PDH signal and the output of the second circuit is selected when the pure SDH signal is received. A local oscillator produces a first clock signal when the incoming signal contains the PDH signal or a second clock signal when the pure SDH signal is received. A read/write circuit is provided for storing the selected signal into a buffer at a first rate and reading the stored signal from the buffer at a second rate. The difference between the first and second rates is detected by a comparator. A microprocessor-controlled oscillator, which operates in a frequency synthesizer mode when the PDH signal is contained in the incoming signal or in a phase locked mode when the incoming signal is a pure SDH signal, is responsive to the difference value for generating a clock signal whose intervals are averaged during the frequency synthesizer mode and whose intervals are locked to the difference value during the phase locked mode. The output of the microprocessor-controlled oscillator is mixed with either of the first and second clock signals from the local oscillator to produce a line clock signal at which the second rate of the read/write circuit is set.

REFERENCES:
patent: 5471511 (1995-11-01), De Langhe et al.
M. Carbonelli et al., "Synchronization of SDH Networks: Slave Clocks Model and Stability Measures", IEEE Global Telecommunications Conference (Cat. No. 92CH3130-2), pp. 829-833, vol. 2, Feb. 1992.
P. Nowosad et al., "Phase Deviations on SDH and SDH/PDH Interface", Proceedings of the 1993 IEEE South African Symposium on Communications and Signal Processing, pp. 52-57, Sep. 1993.
S. Bregni et al., "Jitter Testing Technique and Results at VC-4 Desynchronizer Output of SDH Equipment", IEEE Instrumentation and Measurement Technology Conference (Cat. No. 94CH3424-9) pp. 1407-1410, Mar. 1994.

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