Microprocessor arithmetic logic unit using multiple number repre

Details Microprocessor arithmetic logic unit using multiple number repre Microprocessor arithmetic logic unit using multiple number repre

1997-07-31

1998-09-29

Mai, Tan V.

Boots, shoes, and leggings

3647462, 36471602, G06F 738, G06F 700

Patent

active

058154205

ABSTRACT:
A microprocessor (5) having at least one arithmetic logic unit, or ALU, (42) for operating upon operands of multiple number representation types is disclosed. The ALU (42) includes a binary logical unit (52) for performing logical operations upon operands in a binary representation, and an arithmetic unit (50, 50') for performing arithmetic operations upon operands in a redundant number representation. The redundant number representation is of a type that may be operated upon by adder circuitry such as signed-digit adders or carry-save adders, where carry information need not propagate along the entire operand. A register file (39, 39') is provided, which stores each operand in both the binary form and in the redundant number representation; a valid bit (V) is provided in combination with the binary portion of each entry in the register file (39, 39'). Upon execution of a logical operation, the result is written back into the register file (39, 39') in both the binary and redundant forms, setting the valid bit to indicate that the binary form is valid. Upon execution of an arithmetic instruction, the binary form of the result is not immediately available; the redundant representation of the result is written back, with the valid bit cleared. Conversion of the result in the redundant representation to the binary form may be done in the next machine or instruction cycle by conversion circuitry (60, 60').

REFERENCES:
patent: 4890127 (1989-12-01), Darley
patent: 5680339 (1997-10-01), Moyse et al.
patent: 5696954 (1997-12-01), Guttag et al.

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