Inter-chip bus structure for moving multiple isochronous data st

Details Inter-chip bus structure for moving multiple isochronous data st Inter-chip bus structure for moving multiple isochronous data st

1996-10-21

1999-04-27

Sheikh, Ayaz R.

395309, G06F 1300

Patent

active

058988483

ABSTRACT:
A method for communicating to a plurality of peripheral devices in a computer system, the computer system comprising a first expansion bus, a bus bridge for coupling to the first expansion bus and for interfacing to a second bus, a second bus coupled to the bus bridge, and a plurality of peripheral devices connected to the second bus. The method includes activating a source port in the bus bridge to configure the source port in the bus bridge for a transfer. Next, the bus bridge receives and stores an address from the first expansion bus in a source port of the bus bridge. The address identifies a destination port on one of the plurality of peripheral devices. The bus bridge then receives and stores data from the first expansion bus in a buffer. The data is to be sent to the destination port. The bus bridge then transmits one or more address/data pairs to the destination port of the peripheral device. The address/data pairs each includes the address received from the first expansion bus and the data received from the first expansion bus. The transmitting is performed automatically in response to receiving the data from the first expansion bus when the source port is activated.

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PCI Local Bus Multimedia Design Guide, Revision 1.0, Mar. 29, 1994, pp. 1-40.
Peripherial Components, Intel, 1995, pp. ix, 1-1 through 1-72.

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