CRC code generation circuit, code error detection circuit, and C

Details CRC code generation circuit, code error detection circuit, and C CRC code generation circuit, code error detection circuit, and C

1997-03-21

1999-04-27

Elmore, Reba I.

Excavating

371 376, G06F 1110

Patent

active

058987126

ABSTRACT:
When encoding data bits in a CRC code word and "0" information is received for every bit by a dividing circuit, the CRC code word is divided by a generation polynomial and remainder data resulting from the division is output from parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value in the adder to produce a sum. The sum is a CRC code in a CRC code word for transmission. When a code error is detected, data having a plurality of bits in a CRC code word and a CRC code are received by the dividing circuit, where they are divided by the generation polynomial and remainder data is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder to produce a sum, and the sum is processed into a logical sum in a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.

REFERENCES:
patent: 4238852 (1980-12-01), Iga et al.
patent: 4630271 (1986-12-01), Yamada
patent: 4910736 (1990-03-01), Tanaka et al.

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