Single event upset detection and protection in an integrated cir

Details Single event upset detection and protection in an integrated cir Single event upset detection and protection in an integrated cir

1997-05-15

1999-04-27

Tu, Trinh L.

Excavating

371 221, 361729, 340679, G06F 1100

Patent

active

058987118

ABSTRACT:
Secure operations within an integrated circuit are protected. In order to perform the protection a plurality of single event upset detectors are distributed within the integrated circuit. The single event upset detectors include bit-registers. Each of the plurality of the single event upset detectors is monitored for a single event upset. When a single event upset in any of the single event upset detectors is detected, an error condition is indicated.

REFERENCES:
patent: 4365332 (1982-12-01), Rice
patent: 4414669 (1983-11-01), Heckelman et al.
patent: 4585932 (1986-04-01), Roberts et al.
patent: 4959772 (1990-09-01), Smith et al.
patent: 5389738 (1995-02-01), Piosenka et al.
patent: 5596716 (1997-01-01), Byers

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