Television – Bandwidth reduction system – Data rate reduction
Patent
1996-05-03
1998-09-29
Britton, Howard
Television
Bandwidth reduction system
Data rate reduction
348423, 348845, 381 2, 704504, H04N 736, H04N 750
Patent
active
058152067
ABSTRACT:
Disclosed is a partitioning procedure for designing MPEG decoders, AC-3 decoders, and decoders for other audio/video standards. The procedure provides that some specified decoding functionality be implemented exclusively in the form of hardware and certain other specified decoding functionality be provided exclusively as firmware or software. A video decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, video header processing functions; and (b) hardware for implementing preparsing assist, macroblock reconstruction, and video display control functions. An audio decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, decoding fields containing parameters for processing the audio data; and (b) hardware for implementing matrixing and windowing functions on the audio data.
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Dave Bursky, "Single Chip Performs Both Audio and Video Decoding," Electronic Design, Apr. 3, 1995.
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Chau Kwok K.
Malladi Srinivasa R.
Miller Marc A.
Britton Howard
LSI Logic Corporation
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