Digital clock recovery circuit apparatus

Pulse or digital communications – Repeaters – Testing

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375 95, 375119, 328109, 329104, H03K 519

Patent

active

046352775

ABSTRACT:
A digital circuit which ascertains the middle of a digital pulse by first determining its total length through digital logic means in combination with a digital signal delay means, and uses this information to operate a state machine (or sequencer), which will assume that data clocks occur at the time of the last received valid data pulse until new logic "1" data is received, and at this time can be resynchronized or phase-locked if there is a time discrepancy between recently received data and the status of the state machine.

REFERENCES:
patent: 4412339 (1983-10-01), Alfke et al.
patent: 4571514 (1986-02-01), Nelson et al.
patent: 4571735 (1986-02-01), Furse

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