Computer implemented method for compressing 24 bit pixels to 16

Details Computer implemented method for compressing 24 bit pixels to 16 Computer implemented method for compressing 24 bit pixels to 16

1996-12-17

1999-04-27

Moise, Emmanuel L.

Boots, shoes, and leggings

382233, 382235, 395102, 395109, 395112, G06F 700, G06F 1500

Patent

active

058986014

ABSTRACT:
A computer implemented method for compressing bit formats provided in a first packed data sequence. One embodiment of the method comprises the steps of generating, in response to executing a first instruction, a second packed data sequence by copying the first packed data sequence. A second step of masking, in response to executing a second instruction, a portion of the first packed data sequence. A third step of shifting data elements of the first packed data sequence, in response to executing a third instruction, wherein the data elements are independently shifted by separate shift counts. A fourth step of masking, in response to executing a fourth instruction, a portion of the second packed data sequence. A fifth step of generating, in response to executing a fifth instruction, a final result by joining the second and first packed data sequences.

REFERENCES:
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4393468 (1983-07-01), New
patent: 4418383 (1983-11-01), Doyle et al.
patent: 4498177 (1985-02-01), Larson
patent: 4633483 (1986-12-01), Takahashi et al.
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4771379 (1988-09-01), Ando et al.
patent: 4989168 (1991-01-01), Kuroda et al.
patent: 5095457 (1992-03-01), Jeong
patent: 5187679 (1993-02-01), Vassiliadis et al.
patent: 5218431 (1993-06-01), Gleicher et al.
patent: 5287420 (1994-02-01), Barret
patent: 5446831 (1995-08-01), Yamashita et al.
J. Shipnes, Graphics Processing with the 88110 RISC Microprocessor, IEEE (1992), pp. 169-174.
MC88110 Second Generation RISC Microprocessor User's Manual, Motorola, Inc. (1991).
Errata to MC88110 Second Generation RISC Microprocessor User's Manual, Motorola Inc. (1992), pp. 1-11.
MC88110 Programmer's Reference Guide, Motorola Inc. (1992), pp. 1-4.
i860.TM. Microprocessor Family Programmer's Reference Manual, Intel Corporation (1992), Ch. 1,3,8,12.
R.B. Lee, Accelerating Multimedia Wtih Enhanced Microprocessors, IEEE Micro (Apr. 1995), pp. 22-32.
TMS320C2x User's Guide, Texas Instruments (1993) pp. 3-2 through 3-11; 3-28 through 3-34; 4-1 through 4-22; 4-41; 4-103; 4-199 through 4-120; 4-122; 4-150 through 4-151.
L. Gwennap, New PA-RISC Processor Decodes MPEG Video, Microprocessor Report (Jan. 1994), pp. 16, 17.
SPARC Technology Business, UltraSPARC Multimedia Capabilities On-Chip Support for Real-Time Video and Advanced Graphics, Sun Microsystems (Sep. 1994).
Y. Kawakami et al., LSI Applications: A Single-Chip Digital Signal Processor for Voiceband Applications, Solid State Circuits Conference, Digest of Technical Papers; IEEE International (1980).
B. Case, Philips Hopes to Displace DSPs with VLIW, Microrprocessor Report (Dec. 94), pp. 12-15.
L. Gwennap, UltraSparc Adds Multimedia Instructions, Microprocessor Report (Dec. 94), pp. 16-18.
N. Margulis, i860 Microprocessor Architecture, McGraw Hill, Inc. (1990) Ch. 6,7,8,10,11.
Pentium Processor User's Manual, vol. 3: Architecture and Programming Manual, Intel Corporation (1993), Ch. 1,3,4,6,8, and 18.

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