Scaleable very long instruction word processor with parallelism

Details Scaleable very long instruction word processor with parallelism Scaleable very long instruction word processor with parallelism

1994-12-09

1997-02-04

Harrell, Robert B.

395800, G06F 945

Patent

active

056008104

ABSTRACT:
A system is provided to increase the efficiency of a VLIW, Very Long Insttion Word, processor which matches its level of parallelism, LOP, to the LOP of the executable code before executing the code's fixed-length VLIW instructions, so that object-level code compatibility is kept for different processor implementations of the same VLIW architecture required for different applications. Matching is accomplished either by reducing the LOP of the processor via inactivating the processor's functional units, or by effectively reducing the LOP of the executable code via the processor executing the sequential portions of each VLIW instruction in the code, with the length of the portions equal to or less than the number of operations that the processor can handle as a VLIW instruction.

REFERENCES:
patent: 5347639 (1994-09-01), Rechtschaffen et al.
patent: 5408658 (1995-04-01), Rechtschaffen et al.
patent: 5502826 (1996-03-01), Vassiliadis et al.

Affiliated with

Also associated with

Rating

Scaleable very long instruction word processor with parallelism does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scaleable very long instruction word processor with parallelism , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scaleable very long instruction word processor with parallelism will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-688429