Patent
1985-12-30
1987-06-16
Larkins, William D.
357 239, 357 41, 357 51, 357 59, H01L 2348
Patent
active
046739696
ABSTRACT:
A semiconductor device having a pair of wiring layers connected in parallel with each other in which a first wiring layer is formed over a semiconductor substrate through a insulation layer. The first wiring layer is made of poly-Si and has relatively high resistivity. Therefore a second wiring layer is formed over the first wiring layer through an insulation layer. A portion of the second wiring layer has low conductivity and is parallel connected to the first wiring layer in order to reduce the resistivity of the wiring layer. Another portion of the second wiring layer has low conductivity and is used as resistive means.
REFERENCES:
patent: 4163246 (1979-07-01), Aomura et al.
patent: 4222062 (1980-09-01), Trotter et al.
patent: 4240097 (1980-12-01), Raymond, Jr.
patent: 4278989 (1981-07-01), Baba et al.
patent: 4329706 (1982-05-01), Crowder et al.
Ariizumi Shoji
Segawa Makoto
Kabushiki Kaisha Toshiba
Larkins William D.
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