Method of forming a DRAM stacked capacitor with a two step ladde

Fishing – trapping – and vermin destroying

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437919, 437977, H01L 218242

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active

058145265

ABSTRACT:
The present invention provides a method of manufacturing a capacitor having a two step ladder cross sectional shape. The method begins by forming a first conformal layer and a first insulation layer over a substrate. A contact hole is opened through the first conformal layer and the first insulation layer. A first conductive layer and a first masking layer are formed over the first insulation layer and in the contact opening. Then, the first masking layer and the first conductive layer are patterned to form a first ridge over at least portions of the source region. A first dielectric layer composed of silicon oxide is then formed over the first conductive layer. The first dielectric layer is anisotropically etched to form spacers on the sidewalls of the ridge. The first conducive layer and the first masking layer are anisotropically etched using the spacers as an etch mask thereby forming the storage electrode having a two step ladder cross sectional shape from the remaining first polysilicon layer. The first masking layer, the spacers, and the first insulation layer are removed. A capacitor dielectric layer and a top plate electrode are formed over the storage electrode to form the capacitor. The storage electrode with the two step ladder cross sectional shape reduces the surface topology without reducing capacitance.

REFERENCES:
patent: 5405799 (1995-04-01), Woo et al.
patent: 5451537 (1995-09-01), Tseng et al.
patent: 5468670 (1995-11-01), Ryou
patent: 5492849 (1996-02-01), Pork

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