Patent
1995-12-28
1998-05-05
Bowler, Alyssa H.
395555, 39580001, 395898, G06F 1338
Patent
active
057489173
ABSTRACT:
A data system architecture and interface circuits permit slow devices having limited signal capacities to launch and receive information from a central bus. Data is clocked onto the bus with a master circuit at the leading and trailing edges of the bus clock so that portions of a large multibit signal are launched without having to wait for the initiation of a next clock cycle. Accordingly, data portions are launched during both leading and trailing edges of the clock signal. In the case of a simple bus device not able to accommodate inclusion of a slave interface circuit, the received signal packet is provided in adapted form anticipating that only a second half portion of the signal packet will actually be registered as received.
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Flaig Charles M.
Kelly James D.
Krein William Todd
Apple Computer Inc.
Bowler Alyssa H.
Davis Jr. Walter D.
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