Phase lock loops and methods for their operation

Details Phase lock loops and methods for their operation Phase lock loops and methods for their operation

1993-02-18

1994-08-02

Nelli, Raymond A.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, H03L 700

Patent

active

053349512

ABSTRACT:
A phase lock loop comprises a voltage controlled oscillator, a phase detector and a loop filter comprising a charge pump and a filter network. The voltage controlled oscillator generates an output signal having a frequency which is responsive to a control voltage. The phase detector is responsive to the output signal and to a reference signal to generate a control signal indicative of a phase difference of the output signal and the reference signal. The charge pump is responsive to the control signal and to the control voltage to apply a charge indicative of both the phase difference and the control voltage to the filter network to develop the control voltage. Because the charge supplied by the charge pump depends on the control voltage as well as the phase difference of the output signal and the reference signal, the rate of adjustment of the output signal frequency depends on the present output signal frequency. Consequently, there is a normalization of performance with respect to operating frequency which provides more stable and predictable performance characteristics over a given range of operating frequencies.

REFERENCES:
patent: 4857866 (1989-08-01), Tateishi
patent: 4885552 (1989-12-01), Boudewijns
patent: 5103191 (1992-04-01), Werker
patent: 5121085 (1992-06-01), Brown
patent: 5136253 (1992-08-01), Ueno
patent: 5136260 (1992-08-01), Yousefi-Elezei
patent: 5208555 (1993-05-01), Graham et al.
patent: 5257294 (1993-10-01), Pinto et al.
patent: 5278520 (1994-01-01), Parker et al.
"Design of PLL-Based Clock Generation Circuits", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.

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