Digital phase locked loop clock recovery scheme

Details Digital phase locked loop clock recovery scheme Digital phase locked loop clock recovery scheme

1987-11-19

1989-04-11

Pellinen, A. D.

Pulse or digital communications

Spread spectrum

Direct sequence

375 83, 375106, H03D 324

Patent

active

048212970

ABSTRACT:
A digital clock recovery scheme is disclosed. A reference clock, is used to provide a plurality of N signals with different clock phases. The incoming data stream is sampled and clocked with the reference clock to generate a plurality of M samples for each data bit. The logic values of the M samples are then analyzed to determine the relationship between the current clock phase and the data bit transition. In particular, if all samples agree, the clock phase is correctly aligned with the data. If the clock phase is either leading or lagging the data, various samples will disagree. In the latter situation, the clock phase is adjusted until all samples agree, the particular clock which provides this state thus being defined as the recovered clock signal.

REFERENCES:
patent: 3983498 (1976-09-01), Malek
patent: 4218771 (1980-08-01), Hogge, Jr.
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4357707 (1982-11-01), Delury
patent: 4363002 (1982-12-01), Fuller
patent: 4584695 (1986-04-01), Hee Wong et al.
Design of PLL-Based Clock Generation Circuits, Deog-Kyoon Jeong et al., IEEE Journal of Solid-State Circuits, vol. SC-22, Apr. 1987, No. 2.

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