Short term response enhancement for digital phase-locked loop

Details Short term response enhancement for digital phase-locked loop Short term response enhancement for digital phase-locked loop

1981-07-10

1984-04-03

Orsino, Jr., Joseph A.

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Control

375120, 328155, 331 11, H03L 718

Patent

active

044411952

ABSTRACT:
A short term response enhancement for a digital phase-locked loop is implemented to provide a relatively major change in the phase of the output signal over a relatively short period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur, producing an output signal when the two numbers agree. The number of pulses which occur between successive cycles of the input signal are also compared against the previously determined average. A count which differs from the average count indicates a change in phase of the input signal. The present invention takes the absolute value of the measured error and, based upon the prior modification made during the previous two cycles of the input signal to the count sequence modifies the count sequence of the counter which is counting the number of pulses from the last output signal, by either adding one or subtracting one from the count sequence, thereby effecting a relatively major change in the phase of the output signal over a relatively short period of time.

REFERENCES:
patent: 4242639 (1980-12-01), Boone
patent: 4375694 (1983-03-01), Kuhn

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