Static information storage and retrieval – Floating gate – Multiple values
Patent
1999-06-07
2000-08-01
Nelms, David
Static information storage and retrieval
Floating gate
Multiple values
36518518, 36518523, G11C 1134
Patent
active
060976284
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to a multi-level type of memory circuit for binary information.
Memories of this type are usually termed "non-volatile" because of their capability to retain stored information over very long time periods, even in the absence of a power supply, and include the EPROM, EEPROM, and FLASH EEPROM families.
BACKGROUND OF THE INVENTION
Known own from U.S. Pat. Nos. 5,218,569 and 5,394,362 are multi-level non-volatile memories of this type. The construction of a FLASH EEPROM multi-level memory is also described in an article TA 7.7, "A Multilevel Cell 32Mb Flash Memory", ISSCC95 Conference, Feb. 16, 1995.
These publications also address and solve the problem of programming or writing by a cyclical repetition of program pulses and verification steps; specifically, a cell to be written into is applied, between its gate and source terminals, a voltage write pulse from a row decoding circuit which is power ed by a supply circuit. The cell is then read from to verify the level of its threshold voltage and decide on whether a new pulse is to be applied thereto or the programming brought to an end.
The above article postulates a four-level program and a distribution of the threshold voltages of approximately 500 mV for each level. This involves a spacing of about 500 mV between levels, for a supply voltage of about 3.3 V to the integrated electronic storage device.
If the supply voltage were lower, as is in the wish of so many manufacturers of electronic apparatus for telecommunications applications, for example, such values would have to be reduced, and be reduced still further as the number of the levels increases.
The provision of distributions so narrow and levels so close together requires extended programming times, because the number of the program cycles has to be increased, as well as highly sophisticated and complex read circuits.
This invention is based on the observation that, when a set of non-volatile memory cells having a given distribution of threshold voltages are subjected to the same electrical "treatment", the distribution remains near-constant and shifts in voltage by an amount not determinable with any great accuracy.
This invention proposes, therefore, of arranging for the write operations to be electrically identical for all the cells; this being accomplished by so regulating the write voltage as to make it independent of at least the supply voltage.
To avoid read errors due to shifting inaccuracy, it would be of advantage if the levels could be well spaced apart; this being obtained by generating a high write voltage internally with respect to the supply voltage.
With the levels well spaced apart, the write operation is less critical, and can be carried out advantageously with a single pulse of properly regulated width and duration.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more clearly appreciated from the following description, to be read in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates cell characteristics vs. associated levels and gain variations;
FIG. 2 illustrates the architectures of a conventional electronic storage device and one according to the invention;
FIG. 3 shows distributions of cell threshold voltages vs. associated levels; and
FIGS. 4 and 5 show first and second circuit diagrams for part of a generating circuit according to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 depicts an ideal situation in which the cells associated with one level have exactly the same threshold voltage. In the instance of FIG. 1, there are tour discrete levels DL0, DL1, DL2, DL3 provided which are associated with four discrete cell threshold voltage values L0, L1, L2, L3. This can only be obtained by adopting extremely complicated write and erase methods, and such a situation can at best be approached in actual practice.
Irrespective of the method used, the characteristics of the various cells associated with one level are bound to be different because the manufacture of integrated
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Galanthay Theodore E.
Ho Hoai V.
Nelms David
STMicroelectronics S.r.l.
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