Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1981-11-20
1984-04-03
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307279, 307362, 307530, 365230, H03K 19094, H03K 1704, H03K 3356, G11C 800
Patent
active
044410395
ABSTRACT:
An address input buffer for a cross-coupled latch of the type including two switching transistors with output nodes "a" and "b". The address input buffer circuit structure includes a first depletion device having its source electrode connected to latch node "b" and the address input voltage connected to its gate, and a second depletion device having its source electrode connected to latch node "a" and to its gate so that the voltage differential across the latch is a function of the variable current difference between the two depletion devices because the gate to source voltage of one depletion device is constant and the gate to source voltage of the other depletion device is variable in accordance with the level of the address input voltage. Thus, the address input voltage is not compared to a fixed reference voltage, and no capacitive boosting of a reference and address voltage is necessary to turn on the latch. Embodiments of the address input buffer circuit for both static and dynamic random access memory applications are also disclosed.
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Love, "FET Circuit for Receiving Weak Input Signals"; IBM Tech. Discl. Bull; vol. 21, No. 6, pp. 2590; 11/78.
Furman, "Address Buffer True/Complement Generator"; IBM Tech. Discl. Bull; vol. 18, No. 11, pp. 3597-3598; 4/76.
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"Depletion-Mode FET load Devices Switched with Positive Signal Voltage Levels".
IBM Technical Disclosure Bulletin vol. 20, No. 9 2/78 p.3647 by Cecchi et al " Bipolar/FET Sense Latch for Storage Array".
Anagnos Larry N.
Goodwin John J.
International Business Machines - Corporation
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