Direct-coupled PNP transistor pull-up ECL circuits and direct-co

Details Direct-coupled PNP transistor pull-up ECL circuits and direct-co Direct-coupled PNP transistor pull-up ECL circuits and direct-co

1992-11-13

1994-08-02

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, 307443, H03K 19086, H03K 19003

Patent

active

053348869

ABSTRACT:
An emitter coupled logic circuit includes a series connected PNP transistor and diode to improve the pull-up delay and power consumption. The biasing of the PNP transistor is established by utilizing existing voltage levels in the emitter coupled logic circuit with no extra biasing circuit and power. Complementary push-pull emitter coupled logic circuit configurations with no power wasted in the biasing of the push-and-pull transistors can be derived based on this PNP pull-up scheme and NPN active-pull-down scheme.

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C. T. K. Chuang "High-Speed/Low-Power Charge-Buffered Active-Pull-Down ECL/NTL Circuts" IBM Technical Disclosure Bulletin, vol. 33, No. 1A, Jun. 1990, pp. 470-472.
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