Floating-point systolic array including serial processors

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G06F 748

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active

048721336

ABSTRACT:
A systolic array including chips having interface and timing and control circuitry and a plurality of processing elements. Each of the processing elements includes a floating-point serial processor and a plurality of data storage registers. The data storage registers in all of the elements communicate through a gridwork of data buses and all data registers and processing elements are programmed through a global bus. Software is simplified because algorithms are implemented directly in the new architecture.

REFERENCES:
patent: 3701976 (1972-10-01), Shively
patent: 4751665 (1988-06-01), Cappello et al.
Blackmer et al., "A 200 MOPS Systolic Processor", SPIE Conf. Proceeding, vol. 298, Real Time Signal Processing IV, Aug. 81, p. 9.

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