Memory bus architecture

Details Memory bus architecture Memory bus architecture

1987-07-06

1988-07-12

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1340, G06F 1342

Patent

active

047574399

ABSTRACT:
A memory bus architecture uses a standard unified bus, microprocessor system, and separate memory bus. Access to memory banks coupled to the memory bus may be made by subsystems communicating over the unified bus using the standard protocol of the unified bus, or may be made by the microprocessor using an access protocol method wherein an accessed memory bank generates an acknowledgement signal upon receipt of a READ or WRITE command rather than after the completion of the respective READ or WRITE operation. A further aspect is an Early READ/WRITE circuit that rapidly detects the initiation of a READ or WRITE command by the microprocessor by decoding standard microprocessor status signals in order to generally commence a READ or WRITE operation prior to the time that a normal READ or WRITE operation would be commenced.

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Intel, pp. B-101 to B-119, Aug. 1981, (Intel 8288 and 8289 Devices).
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MacKenna et al., "Backup Support Gives VME Bus Powerful Milti-Processing Architecture", 3/22/84, Electronics, pp. 132-138.
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Boberg, "Major Standardization Issues of the Proposed IEEEE 796 Bus-Multibus", 11/82, vol. 6, No. 9, pp. 471-474.
Philipson et al., "A Communication Structure for a Multiprocessor Computer With Distributed Global Memory", 1983, ACM, pp. 334-340.

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