Phase locked loop circuit for eliminating impulses in output dat

Details Phase locked loop circuit for eliminating impulses in output dat Phase locked loop circuit for eliminating impulses in output dat

1998-02-03

2000-08-01

Kinkead, Arnold

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 375376, 327159, 360 51, H03L 708, H03L 7085

Patent

active

060972556

ABSTRACT:
A phase-locked loop circuit adapted to follow up with the phase of an input signal includes a phase comparator 150 for phase-comparing, in synchronism with pre-set operating clocks, an input reference signal to an input signal entered as a counterpart for comparison. Since a first detector 154, a second detector 155 and JK-flip-flops 162, 163 output data responsive to pre-set operating clocks, there is produced no phase lag between NU data and ND data nor the phase lag between two tri-state logical outputs. In a conventional system, the phase lag between NU data and ND data was generated due to the differential delay of the input data caused by looped or the feedback components. Since the two input signals, namely the reference signal and the input signal, are phase-compared to each other in synchronism with the pre-set operating clocks, the comparison data obtained as a result of the phase comparison are outputted at a pre-set period thus reducing the malfunctions otherwise produced in the entire circuit.

REFERENCES:
patent: 4600994 (1986-07-01), Hayashi
patent: 4773085 (1988-09-01), Cordell
patent: 5166644 (1992-11-01), Saito et al.

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