Patent
1985-07-03
1988-07-12
Clawson, Jr., Joseph E.
357 15, 357 16, 357 56, H01L 2980
Patent
active
047573589
ABSTRACT:
An FET transistor is provided having a two element semiconductor channel region between metal contacts and epitaxial therewith a graded three element seminconductor, in which two of the three elements are in common with the semiconductor of the channel, positioned between a Schottky barrier gate of the same contact metal and the channel. An FET with a GaAs channel between tin source and drain contacts, a graded 500 to 1000 Angstrom thick GaAlAs region epitaxial with the channel and a Schottky barrier tin metal gate over the GaAlAs region.
REFERENCES:
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patent: 4173764 (1979-11-01), De Cremoux
patent: 4194935 (1980-03-01), Dingle et al.
patent: 4236166 (1980-11-01), Cho et al.
W. Dumke et al., "GaAs FETs W. Self-Reg. Gates", IBM Tech. Discl. Bull., vol. 14, #4, Sep. 1971, pp. 1248-1249.
Hovel Harold J.
Woodall Jerry M.
Clawson Jr. Joseph E.
International Business Machines - Corporation
Riddles Alvin J.
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