Methodology for developing product-specific interlayer dielectri

Details Methodology for developing product-specific interlayer dielectri Methodology for developing product-specific interlayer dielectri

1995-06-23

1997-09-09

Breneman, R. Bruce

Semiconductor device manufacturing: process

With measuring or testing

216 84, 36446828, 438 16, H01L 21306

Patent

active

056651996

ABSTRACT:
A method for developing and characterizing a polish process for polishing an interlayer dielectric (ILD) layer for a specific product or a specific patterned metal layer is provided. A statistically-based model for ILD planarization by chemical mechanical polish (CMP) is used as a guide to determine, in an empirical manner, the proper amount of ILD polishing that will be required to planarize an ILD layer. The statistically-based model also shows the resulting ILD thicknesses to be expected. By relating the blank test wafer polished amount to the maximum amount of oxide removed from the field areas in the die and the total indicated range across the die, the ILD deposition thickness can be adjusted to attain the desired planarized ILD thickness. The attainment of local planarity, however, must be confirmed by an independent measurement technique. The polish process development methodology is extendible with respect to minimum interconnect feature size. This polish process development methodology can also be applied to products requiring multiple planarizations for multiple levels of interconnects.

REFERENCES:
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patent: 5298110 (1994-03-01), Schoenborn et al.
patent: 5391258 (1995-02-01), Brancaleoni et al.
Stell, M. et al. "Planarization ability of chemical mechanical planarization (CMP) processes" Advanced Metallization for Devices and Circuits-Science, Technology and Manufacturability Symposium, MRS proceedings, vol. 337, pp. 151-156. Apr. 1994.
Landis, H. et al. "Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing" Thin Solid Films, vol. 220 pp. 1-7 Nov. 1992.
Boning, D. et al. "Statistical metrologyof interlevel dielectric thickness variation"0 Proceedings of the SPIE, vol. 2334, pp. 316-327 Oct. 1994.

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