Fishing – trapping – and vermin destroying
Patent
1993-08-18
1995-04-18
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 41, 437200, 437909, H01L 21265
Patent
active
054078377
ABSTRACT:
This is a method of fabricating a transistor on a wafer. The method comprises: forming a doped silicon layer; patterning the active transistor regions of the doped silicon layer and utilizing a silicon etch to remove the non-transistor regions of the doped silicon layer to create a silicon mesa; forming a gate oxide layer on a doped silicon mesa; depositing a polysilicon layer on top of the oxide layer; depositing a photoresist layer over the polysilicon mesa; patterning the photoresist layer with a gate configuration; etching to remove portions of the polysilicon layer using the photoresist as a mask to create a polysilicon gate; depositing a TEOS layer over the polysilicon gate and exposed gate oxide; etching to remove portions of the TEOS layer and the exposed gate oxide to leave sidewall spacers on sides of the polysilicon gate and sides of silicon mesa; depositing a metal layer over remaining portions of the polysilicon gate, the sidewall spacers, and the silicon mesa; annealing the wafer to react portions of the metal layer with exposed portions of the silicon mesa to form a metal silicide; etching all unreacted the metal layer to leave the silicided portions of the polysilicon gate and silicided portion of the doped silicon layer.
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patent: 4882297 (1989-11-01), Blossfeld
patent: 5075251 (1991-12-01), Torres et al.
patent: 5185280 (1993-02-01), Houston et al.
patent: 5252502 (1993-10-01), Havemann
Wolf, "Silicon Processing for the VLSI ERA", vol. II; pp. 194-199, 1990.
Booth Richard A.
Chaudhuri Olik
DeLeon Ruben C.
Donaldson Richard L.
Kesterson James C.
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