Method and apparatus for zero extension and bit shifting to pres

Details Method and apparatus for zero extension and bit shifting to pres Method and apparatus for zero extension and bit shifting to pres

1994-11-02

1996-10-08

Donaghue, Larry D.

Boots, shoes, and leggings

395375, 364DIG1, 3642551, 3642557, 364259, G06F 700

Patent

active

055640567

ABSTRACT:
Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.

REFERENCES:
patent: 4959779 (1990-09-01), Weber et al.
patent: 5185872 (1993-02-01), Arnold et al.
patent: 5420992 (1995-05-01), Killian
patent: 5442577 (1995-08-01), Cohen
patent: 5467476 (1995-11-01), Kawasaki
patent: 5471633 (1995-11-01), Colwell et al.

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