Semiconductor overload protection structure

Details Semiconductor overload protection structure Semiconductor overload protection structure

1978-03-08

1980-02-19

Wojciechowicz, Edward J.

357 13, 357 23, 357 41, H01L 2702

Patent

active

041897390

ABSTRACT:
An input voltage overload protection semiconductor structure useful with MOS circuitry consists of a p-region in an n-substrate with p+ type regions formed on both sides of the p-region and an n+ type region centrally located in the p-region. Input signals are applied to the first p+ region. The gate of an MOS structure to be protected from voltage overload is connected to the second p+ type region. A power supply used with the MOS structure is connected to the n+ region. This structure provides significantly greater load protection than the standard resistor-diode-resistor circuit.

REFERENCES:
patent: 3967295 (1976-06-01), Stewart

Affiliated with

Also associated with

Rating

Semiconductor overload protection structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor overload protection structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor overload protection structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-655542