Linking interface system using plural controllable bidirectional

Details Linking interface system using plural controllable bidirectional Linking interface system using plural controllable bidirectional

1986-05-14

1990-01-23

Zache, Raulfe B.

Boots, shoes, and leggings

3642402, 3649354, 36493546, 370 8512, 360825, G06F 1336, G06F 1340, G06F 1342, G06F 1546

Patent

active

048962562

ABSTRACT:
A plurality of data processor components are distributed along a plurality of intracommunication bus systems, each intracommunication bus system having an address bus and each being assigned a unique set of addresses, with at least one of the components associated with each of the intracommunication bus systems including an address signal generator for generating address signals over the address bus of the associated intracommunication bus system. An intercommunication bus system is utilized in combination with a plurality of link interface units, with each link interface unit connected between the intercommunication bus system and a corresponding one of the intracommunicaton bus systems, for carrying out communication of information over the intercommunication bus system between first and second of the intracommunication bus systems, in response to the address signals on the address bus of the corresponding one of the intercommunication bus systems. A related method is also provided.

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Intel Multibus Specification, Intel Corporation, Order No. 9800683-04.

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