Parity processing in arithmetic operations

Details Parity processing in arithmetic operations Parity processing in arithmetic operations

1978-12-15

1980-09-23

Atkinson, Charles E.

Boots, shoes, and leggings

371 49, G06F 1110

Patent

active

042246814

ABSTRACT:
Method and apparatus for parity checking of data, particularly in relation to data used and/or generated by an arithmetic logic unit of a data processing system. Parity is generated for all operations but examined only in connection with those operations which results in valid parity. For these operations which do not directly result in valid parity, parity is ignored. A "parity valid" bit is associated with those operations which generate valid parity and a parity error is indicated only when the parity valid bit occurs at the same time as a parity error.

REFERENCES:
patent: 3531631 (1970-09-01), Burgess
patent: 3751646 (1973-08-01), Geng et al.
patent: 3806716 (1974-04-01), Lahti et al.
Williams, Parity-Check Generate Circuit, IBM Technical Disclosure Bulletin, vol. 12, No. 4, Sep. 1969, p. 623.

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