Digital signal processor with on-chip select decoder and wait st

Details Digital signal processor with on-chip select decoder and wait st Digital signal processor with on-chip select decoder and wait st

1993-09-27

1998-04-14

Gossage, Glenn

39549701, 395405, 395651, 395552, 395558, 395556, 395836, 395879, G06F 1200, G06F 1300, G06F 104

Patent

active

057404046

ABSTRACT:
A digital signal processor (DSP) provides an improvement in the interfacing and sharing of external memory devices. Specifically, the digital signal processor is provided with a parallel interface for communicating with external memory devices, a chip select decoder located on-chip for selectably enabling external memory devices, and a wait status controller for holding processor operation until the selected memory device is ready. The memory architecture is configurable for internal or external wait state generation and memory sharing with other DSPs so that a plurality of varying speed memory devices may be accessed. The chip select decoder includes a programmable register for storing a mode configuration word for defining a plurality of external memory configurations.

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