Dynamic type semiconductor memory device having an error checkin

Details Dynamic type semiconductor memory device having an error checkin Dynamic type semiconductor memory device having an error checkin

1988-12-22

1991-04-30

Smith, Jerry

Excavating

371 404, G06F 1110

Patent

active

050124722

ABSTRACT:
In a memory cell comprising a data cell array and a parity cell array, an error checking.multidot.correcting circuit is connected to each of the arrays through a selector. The selector is constituted by transistors connected to each of the bit lines in the memory cell. The number of circuit elements constituting the error checking.multidot.correcting circuit corresponds to one-half of the number of the bit line pairs included in the data cell array and the parity cell array. In an error correcting mode, half of the data appeared on the bit line pairs in data cell array and the parity cell array are transferred to the error checking.multidot.correcting circuit by the selector, so that the errors are corrected. Thereafter, the data of the remaining half of the bit line pairs are processed in the same manner. Therefore, the number of circuit elements of the error checking.multidot.correcting circuit can be reduced compared with the prior art, improving the degree of integration of the device.

REFERENCES:
patent: 4380812 (1983-04-01), Ziegler
patent: 4692923 (1987-09-01), Poeppelman
patent: 4703453 (1987-10-01), Shinoda
patent: 4758989 (1988-07-01), Davis
patent: 4780875 (1988-10-01), Sakai
H. Davis, "A Word Wide 1Mb ROM with Error Correction", IEEE Int. Solid State Circuit Con., pp. 40-41, 2/1985.
J. Yamada, "Selector-Line Merged Built-In ECC Technique for DRAM's", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, pp. 868-873, 10/1987.

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